Integration density of a memory cell in a semiconductor device is on the rise due to growing demands for higher capacity. In case of a memory cell in DRAM, which includes a MOS transistor and a capacitor, higher integration density thereof results in a reduction of capacitor region. Consequently, as the area of the capacitor is reduced, the electrostatic capacity thereof is also reduced.
As current state of the art, Ta2O5 (tantalum pentaoxide) or Si3N4 (silicon nitride) has been conventionally used for its high dielectric constant in fabricating capacitors in semiconductors. Recent growth in demands for dielectric material having higher dielectric constant has been reflected in the field of research in developing capacitors yielding high capacitance at a low voltage. In case of DRAM having a high integration density, since it is important to reduce the area of a capacitor, many studies have been done to replace Ta2O5 and Si3N4 with materials such as BST (barium strontium titanate), PZT (lead zirconium titanate) and PLZT (lead lanthanum zirconate titanate) having high dielectric constant.
Further, in an effort to increase the integration density, a trench type capacitor is used in DRAM whereas a stack type capacitor is used in system integrated circuits, which has relatively fewer limitations in terms of the area and voltage requirement, compared to DRAM. However, the system integrated circuits require higher standards in quality in uniformity and frequency dependence than that of DRAM.
However, in order to obtain stable characteristics of the capacitor in a device, e.g., a system integrated circuit, rather than having such a highly dielectric material, it is preferable to use silicon oxide or silicon nitride having an adequate dielectric constant, thereby providing chemical stability. Since spatial limitations are less of a concern in the system integrated circuit than DRAM, adjusting the area of the capacitor or the distance between layers thereof can suitably control its capacitance.
FIG. 1 shows a cross-sectional view of a conventional capacitor in a system integrated circuit.
In a typical capacitor structure, as shown in FIG. 1, an aluminum layer 100 and a TiN layer 102 are sequentially deposited and patterned into bottom electrodes on a substrate 98, which includes MOS transistors (not shown) or the like, and an IMD (inter-metal dielectric) layer 104 is formed on the exposed substrate and the TiN layer 102. Thereafter, via holes 106 and 108 are formed, and are then filled with a conductive material, e.g., W.
Subsequently, a metal-insulator-metal (MIM) stack structure is obtained by sequentially depositing bottom metal layers 110 and 112, an insulation layer 114, and a top metal layer 116. The bottom metal layers 110 and 112 are made of about 3000–10000 Å thick Al and about 600 Å thick TiN, respectively, and formed by sputtering. The TiN layer 102, 112 and 116 also serves as anti-reflection layers as well known in the art. The insulation layer 114 is formed of a silicon nitride fabricated by CVD (chemical vapor deposition) and has a thickness of about 300–600 Å. The top metal layer 116 has a thickness of about 1000 Å.
Thereafter, the insulation layer 114 and the TiN layer 116 are photolithographically defined and patterned to form the capacitor forming region, and then the Al layer 110 and the TiN layer 112 are defined and patterned in the same manner described above. Thereafter, a planarized IMD layer 118 is formed on the structure thus treated.
Subsequently, via holes 120 and 122 are formed and then filled with a conductive material, e.g., W, and thereafter first and second metal lines 124-1 and 124-2 are formed on top portions of the via holes 120 and 122.
The conventional capacitor described above suffers from certain drawbacks. First, the capacitor structure requires rather complex film forming and patterning processes and therefore is costly. That is, the structure necessitates the formation of the TiN layer 112 serving as an ARC (anti-reflective coating) layer, Si3N4 layer 114, and the top capacitor electrode 116.
Consequently, there occurs a great deal of non-uniformity in the thickness of the IMD layers deposited on the capacitor region and the remaining regions, which has an adverse effect on the planarization of the IMD layer and the via etching process. Further, the conventional MIM capacitor structure described above is produced by two etching steps: i.e., one for the layers 116, 114 and the other for the layer 112, thus generating a step between the layers 112 and 114 at which etching residues may be collected, which in turn contributes to the generation of leakage current and deteriorates the characteristics of the capacitor.